1. Field of the Invention
The invention relates to three-dimensional circuits and more particularly to the formation of three-dimensional circuits.
2. Background
Three-dimensional circuits are generally those in which active or passive circuit elements are formed over a surface of a planar substrate. A three-dimensional circuit typically interacts with circuit elements formed in a surface of a substrate. A typical monolithic integrated circuit has transistors and other structures formed at least in part in the substrate. A three-dimensional circuit may rely, for example, for signal operation or function on a substrate, but the operation of the circuit elements do not utilize a portion of the substrate. Implementation of three-dimensional circuit arrays include, but are not limited to, memory arrays, resistor arrays, and transistor arrays.
Commonly-owned, U.S. Pat. No.6,034,882 titled “Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication” and co-pending U.S. patent application Ser. No. 09/560,626, titled “Three-Dimensional Memory Array Method of Fabrication,” describes, in one aspect, three-dimensional circuit arrays such as field programmable, nonvolatile memory arrays wherein circuits are fabricated in a vertical arrangement over rather than in a surface of a planar substrate, such as, for example, a semiconductor substrate.
In many instances, it is desirable from a processing standpoint to construct circuit arrays of multiple levels of similar materials. However, processing techniques such as cell definition through etch patterning often rely on materials of different composition to achieve desired patterning. Thus, what is needed are techniques for forming circuit arrays of similar material that offer consistent performance and distinguishable patterning avenues suitable for use in three dimensional circuit arrays.